2025

  • Dec 01

    Accepted Paper at LLM4Code 26! Our work on zero-shot software vulnerability classification using LLMs has been accepted at LLM4Code 2026 workshop (co-located with ICSE)! In the paper, we explore a RAG-based pipeline that automatically maps detected vulnerabilities to CWE categories, without any task-specific training and while still performing on par with specialized approaches. Led by our KTH master's student Edvin Nordqvist, this paper marks a nice closing chapter for our SEMLA project! 😄

  • Nov 14

    Accepted Paper at Dafny 26! Our work on creating a contamination-free benchmark for formal verification of code has been accepted at the Dafny 2026 workshop (co-located with POPL)! We introduce an automated and reproducible pipeline for Dafny verification benchmarks, along with a public leaderboard for fair model comparison. Check out the current leaderboard here!

  • Nov 06

    New Funded Project! Together with CanaryBit, Ericsson, KTH, Nvidia, Red Hat, and Saab, we will participate in SAFIR, a Vinnova-funded project. The project focuses on securing and strengthening AI-driven cloud-edge infrastructures. It will develop confidential computing, secure high-speed communication, and trustworthy AI-based orchestration.

  • Nov 04

    CoNEXT TPC Invitation. I will serve as a TPC member for the upcoming ACM CoNEXT 2026. Please consider submitting a paper on your latest work!

  • Oct 07

    New Funded Project! I am pleased to announce that Digital Futures will support our EdgeWise demonstrator project on resilient edge robotics. By combining edge computing and verifiable action planning, we aim to improve the safety and responsiveness of next-generation robotic systems. The project is jointly carried out at RISE and KTH.

  • Jul 13

    Accepted Paper at NSDI 26! What if where you store a packet payload could drastically reduce energy use? Our work, Queue-Mem, accepted at USENIX NSDI 2026, reveals that smart payload placement is the key to revolutionizing energy efficiency in terabit-scale NF systems. By cleverly leveraging switch buffer queues, we build the first energy-efficient, high-speed packet pipeline, achieving per-flow processing at Tbps rates using just one commodity server and an ASIC switch.

  • Jul 11

    NPC TPC Invitation. I will serve as a TPC member for the upcoming IFIP NPC 2025. Please consider submitting a paper on your latest work!

  • May 19

    NAMEX Digital Twin Presentation at RIPE 90. At RIPE 90 in Lisbon, Marta Burocchi (NAMEX) and Lorenzo Ariemma (Kathará) presented the IXP Digital Twin infrastructure we are currently developing. The recording is available here.

  • Apr 14

    NetConfEval in Red Hat Research Quarterly. Simone Ferlin-Reiter has written an article showcasing our project, NetConfEval, in the Spring 2025 edition of Red Hat Research Quarterly. You can read the full article here (see page 30).

  • Apr 10

    ICNP TPC Invitation. I will serve as a TPC member for the upcoming IEEE ICNP 2025. Please consider submitting a paper on your latest work!

  • Mar 21

    Accepted Paper in IEEE Network! Our paper proposing a decentralized RL-based forwarding mechanism running on programmable switches for ultra low-latency 6G networks has been accepted in the IEEE Network Magazine!

  • Mar 15

    ANRW TPC Invitation. I will serve as a TPC member for the upcoming ACM/IRTF ANRW 2025. Please consider submitting a paper on your latest work!

  • Mar 01

    NAMEX Digital Twin Article on RIPE NCC Labs & APNIC blog. Marta Burocchi of NAMEX detailed the work carried out on the Digital Twin infrastructure we are currently building. You can read the article both on RIPE NCC Labs and APNIC blog.

  • Mar 01

    NetConfEval in KTH News. Changjie Wang and Prof. Marco Chiesa held an interview with KTH News on the IRTF Applied Networking Research Prize that we won with NetConfEval. The interview can be found here.

  • Jan 14

    IWQoS TPC Invitation. I will serve as a TPC member for the upcoming IEEE/ACM IWQoS 2025. Please consider submitting a paper on your latest work!

  • Jan 08

    IRTF Applied Networking Research Prize! Thrilled to announce that our NetConfEval paper has won the IRTF Applied Networking Research Prize! Out of 69 submissions, it was chosen as one of the top six. Congratulations to Changjie Wang, the recipient of the award!

2024

  • Dec 21

    IPSN TPC Invitation. I will serve as a TPC member for the upcoming IPSN 2025 Workshop (colocated with IEEE/IFIP NOMS 2025). Please consider submitting your interesting ongoing projects!

  • Dec 17

    Three papers accepted at LLM4Code 25! I am super glad to announce that three papers have been accepted in the LLM4Code 2025 workshop (co-located with ICSE)! In the first paper, we explore the possibilities of Transformer-based models in predicting code vulnerabilities from GitHub issues (work led by our former master's student Daniele Cipollone). In the second paper, we are the first to apply domain-specific LLMs pruning, enabling the extraction of efficient sub-models tailored for specific tasks and programming languages (work led by our former master's student Laura Puccioni). Finally, our third paper presents a forward-looking vision on utilizing LLMs to automatically generate formally verified code, paving the way for safer and more reliable software development (work led by Changjie Wang).

  • Dec 11

    Talk at CoNEXT 24. I presented our FAJITA paper on behalf of Hamid Ghasemirahni at ACM CoNEXT 2024 in Los Angeles! If you are interested to know how to scale stateful packet processing beyond 100Mpps, here you can find the video of my presentation.

  • Dec 10

    NetConfEval Shortlisted as Best Paper. Our paper exploring opportunities to utilize LLMs in network configuration tasks has been shortlisted for the Best Paper Award among 38 accepted papers (out of 231 submissions) at ACM CoNEXT 2024! Congrats to the team!

  • Nov 01

    New Position! 🚀 Starting today, I am thrilled to join the Connected Intelligence Unit at RISE as a Senior Researcher! My last two years as a postdoc in the NSLab group at KTH have been invaluable in shaping my growth as a researcher. I am deeply grateful to everyone in the group for their support, encouragement, and the many thought-provoking discussions along the way. I look forward to bringing this valuable experience into my new role and applying it to create meaningful impact. Thank you to everyone who has been part of this journey!

  • Oct 29

    Accepted Paper in IEEE JSAC! An extended version of our NOMS 2024 paper that proposes a new SRv6 behaviour to improve performance of specific traffic classes with stringent latency requirements has been accepted in the IEEE JSAC Journal!

  • Oct 28

    Talk at EuroP4 24. I presented TurboSwitch at EuroP4 2024 in Charleroi! I really enjoyed the lively discussion after the talk. Our idea of deliberately congesting programmable switch queues to boost NF performance sparked a lot of interest among the audience.

  • Sep 19

    Accepted Paper at EuroP4 24! Our paper that explores the unconventional idea of deliberately congesting the queues of a programmable switch to enhance the performance of NFs has been accepted at EuroP4 2024!

  • Jul 27

    ICNP Poster/Demo TPC Invitation. I will serve as a TPC member in the Demo/Poster session for the upcoming IEEE ICNP 2024. Please consider submitting your interesting ongoing projects!

  • Jul 24

    Accepted Paper at CoNEXT 24! Our paper that demonstrates how to push CPU-based packet processors at >100Mpps has been accepted at ACM CoNEXT 2024!

  • Jun 26

    NPC TPC Invitation. I will serve as a TPC member for the upcoming IFIP NPC 2024. Please consider submitting a paper on your latest work!

  • Jun 04

    Ongoing collaboration with NAMEX IXP. Tommaso Caiazzi, Lorenzo Ariemma, and I are actively collaborating with the NAMEX IXP in Rome to create a digital twin of their peering infrastructure entirely built using Kathará! The project was officially announced by Flavio Luciani (NAMEX CTO) during the NAM 2024 event (video in Italian).

  • May 31

    Accepted Paper at CoNEXT 24! Our paper that explores opportunities to utilize Large Language Models (LLMs) in network configuration tasks has been accepted at ACM CoNEXT 2024!

  • May 20

    Featured in MANRS Blog and APNIC blog! A blog post about our ROSE-T project got featured in both MANRS Blog and APNIC Blog!

  • Apr 10

    NSDI TPC Invitation. I will serve as a TPC member for the upcoming USENIX NSDI 2025. Please consider submitting a paper on your latest work!

  • Mar 30

    Accepted Paper at EdgeSys 24! The paper summarizing our efforts to implement an RDMA stack directly on CUDA has been accepted to ACM EdgeSys 2024 Workshop!

  • Mar 26

    Accepted Paper at EuroMLSys 24! Our paper describing how to use Large Language Models (LLMs) to extract useful information from stateful NFs and minmize shared memory accesses has been accepted to ACM EuroMLSys 2024 Workshop!

  • Feb 19

    Interview with KTH News. I held an interview with KTH News on the Best Paper Award that we won at ACM CoNEXT 2023. The interview can be found here in English, and here in Swedish (for reckless people 😊).

  • Feb 15

    IWQoS TPC Invitation. I will serve as a TPC member for the upcoming IEEE/ACM IWQoS 2024. Please consider submitting a paper on your latest work!

  • Jan 11

    ROSE-T Episode in "Between 0x2 Nerds" Podcast. Together with Tommaso and Antonio, we presented ROSE-T in the "Between 0x2 Nerds" podcast hosted by Jeff Doyle and Jeff Tantsura. The recording of the episode can be found here.

2023

  • Dec 23

    Accepted Paper at NOMS 24! Our paper that proposes a new SRv6 behaviour to improve performance of specific traffic classes with stringent latency requirements has been accepted at IEEE/IFIP NOMS 2024! This is a joint work with Tommaso Caiazzi (Roma Tre), Marco Polverini, and Antonio Cianfriani (Sapienza).

  • Dec 05

    Best Paper at CoNEXT! Tommaso Caiazzi, Marco Chiesa and I won the Best Paper Award at ACM CoNEXT 2023 in Paris! In our work, we are the first ones to support millions of low-latency state insertions in programmable ASICs completely from the data plane, pushing what is possible to offload in programmable switches.

  • Dec 01

    Talk at RIPE 89. I presented the ROSE-T project at the 89th RIPE meeting in Rome! ROSE-T is a tool that allows to ensure that router configurations are MANRS-compliant. This is a joint work with Antonio Prado and Tommaso Caiazzi. The presentation can be found here.

  • Nov 06

    IPSN TPC Invitation. I will serve as a TPC member for the upcoming IPSN 2024 Workshop (colocated with IEEE/IFIP NOMS 2024). Please consider submitting a paper on your latest work!